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Nabízená pozice:Digital Design Engineer Vloženo:21. březen 2019 Společnost:Allegro MicroSystems Kontaktní osoba:Monika Benešová Telefon:+420 277 010 200 Místo pracoviště:Praha
Allegro MicroSystems, LLC is a leading provider of linear and angle measurement and current sensing precision analog multi-mode sensors. The company s products form the building blocks of increasingly intelligent automotive sensing applications, enabling advancements in controllability, efficiency, and safety, in the transportation development industry. With a portfolio of intellectual property and a rich history of design and process innovation, Allegro is a trusted partner to leading companies in some of the world s largest markets to include consumer, industrial, and automotive sensors.

Job Overview
At Allegro MicroSystems we architect, design and deploy advanced technology mixed signal sensors. We currently have openings for entry level Digital design engineers to join our expanding advanced sensor development team. This opportunity will allow an individual to contribute within the framework of a broader experienced analog, mixed-signal and digital team. We are looking for a motivated candidate that can leverage the group’s experience to begin quickly contributing to the success of the team.  The primary focus for the individual will be the using cutting edge tools to design state of art sensors in Allegro’s Model Based Design flow for digital signal processing applications. As new product developer, you will be exposed to variety of tools based on specific application requirement, including Mathworks Simulink applications, embedded microprocessor coding, Matlab scripting, Verilog, SystemVerilog and Universal Verification Methodology (UVM).

Job Responsibilities
  • Development of signal processing and control algorithms through system modeling from concept, prototyping, testing and validation to production
  • Traditional Verilog coding / unit level verification of serial interfaces, microprocessor intefaces, SRAM, Flash, EEPROM and the register map
  • Analysis of test results, test coverage and debug of unexpected design behavior. 
  • Synthesis of RTL with timing and area constraints
  • Writing and/or debug of Simulink models using Mathwork tools including Stateflow, HDL coder and digital signal processing tool box

Skills and Experience
  • The successful candidate will possess a Bachelor s / Masters degree in Electrical Engineering - Entry level with 3.0+ GPA 
  • Excellent communication, documentation, problem-solving and analytical skills are required
  • Experience with the use of:  Matlab, Simulink tool set, Verilog, System Verilog, Synthesis, DFT, UVM, embedded microprocessor and FPGA Design and implementation is a plus
  • Exposure to a higher level object oriented language is highly desired (C++, Python, SystemVerilog, etc.). Any exposure to one of the structured verification methodologies is a strong plus
Allegro is committed to equal opportunity employment.

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